As the performance and process limitations on scaling planar transistors are reached, attention has been recently directed to transistor designs having multiple gates (e.g., three-dimensional MOS transistors). In theory, these designs provide more control over a scaled channel by situating the gate around two or more sides of the channel silicon, wherein a shorter channel length can be achieved for the same gate dielectric thickness or similar channel lengths can be used with thicker gate dielectrics.
By alleviating the short channel effects seen in traditional scaled planar transistors, multi-gate designs offer the prospect of improved transistor performance. This is due primarily to the ability to invert a larger portion of the channel silicon because the gate extends on more than one side of the channel. In practice, however, the conventional multi-gate approaches have suffered from cost and performance shortcomings, because Silicon-Over-Insulator (SOI) wafers are more expensive than ordinary silicon substrates, among other reasons.
FIGS. 1A-1E illustrate an example of a prior art manufacturing process for forming a multiple-gate transistor on an SOI wafer. As will be appreciated from these figures and the accompanying discussion, known prior art processes are unable to consistently and effectively isolate the source and drain of a multi-gate transistor from one another.
As shown in FIG. 1A, the prior art process begins with a semiconductor structure 100 from which a multi-gate transistor is formed. The structure 100 is formed over an SOI semiconductor body 101 that includes an insulating layer 102 and a substrate 104. The structure 100 includes a silicon fin 106 in which electrical carriers (i.e., electrons or holes) can propagate. A dielectric 108 is disposed about the fin 106 and separates the fin 106 from a gate electrode 110. The gate electrode 110 may include a first gate electrode layer 112 and a second gate electrode layer 114.
During processing of the transistor, a mask layer (not shown) is deposited over the second gate electrode material 114, and the unmasked portions of the second gate electrode layer are etched away, resulting in the structure shown in FIG. 1B. After the desired portions of the second gate layer 114 have been etched away, another etch 116 with different selectivity is performed to attempt to remove the first gate electrode layer 112, as shown in FIG. 1C. However, as shown in FIG. 1D, prior art processes for etching this first gate electrode layer 112 are insufficient as they to tend to leave residue 118 about the fin 106. As shown in FIG. 1E, this residue 118 is particularly detrimental to the functionality of the multi-gate transistor 120 when the residue is metal, because metal residue can cause the source 122 to be “shorted” to the drain 124. Thus, the metal residue 118 can extend continuously from the source 122 under the patterned gate electrode 110 (e.g., along the vertical surfaces of the fin) and to the drain 124. Because the metal residue 118 is continuous, the source 122 and drain 124 will be coupled to one another and the transistor 120 will not function properly.
Absent the residue 118, during operation, the source and drain associated with the fin could be selectively biased independent of one another, thus creating a potential difference between the source 122 and drain 124. Depending on whether a voltage is applied to the gate electrode 110, electrical carriers either will or will not be freed from the lattice of the fins under the gate electrode 110. Thus, in many respects, a properly constructed multi-gate transistor operates analogously to a traditional planar MOSFET, even though its structure is quite different. As mentioned, if there is residue present, a potential difference may not be able to be established between the source and drain (i.e., because they are “shorted” together), and the transistor may not function properly.
Accordingly, there remains a need for improved transistor devices and manufacturing techniques to realize the advantages of scaling while overcoming the shortcomings of traditional multi-gate transistors.